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Verilog Automatic

by Tian-Changsong ST2/ST3

Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3

Details

  • 2013.08.06.08.11.47
  • github.​com
  • github.​com
  • 6 years ago
  • 2 hours ago
  • 6 years ago

Installs

  • Total 13K
  • Win 9K
  • OS X 2K
  • Linux 2K
Sep 18 Sep 17 Sep 16 Sep 15 Sep 14 Sep 13 Sep 12 Sep 11 Sep 10 Sep 9 Sep 8 Sep 7 Sep 6 Sep 5 Sep 4 Sep 3 Sep 2 Sep 1 Aug 31 Aug 30 Aug 29 Aug 28 Aug 27 Aug 26 Aug 25 Aug 24 Aug 23 Aug 22 Aug 21 Aug 20 Aug 19 Aug 18 Aug 17 Aug 16 Aug 15 Aug 14 Aug 13 Aug 12 Aug 11 Aug 10 Aug 9 Aug 8 Aug 7 Aug 6 Aug 5 Aug 4
Windows 10 5 9 4 2 6 11 5 10 7 4 3 5 7 7 6 9 3 4 8 9 4 7 8 5 3 7 8 4 6 5 8 2 7 8 4 3 1 2 5 6 5 9 4 8 2
OS X 1 1 3 0 2 0 2 1 0 2 1 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 2 0
Linux 4 2 3 1 1 1 2 5 1 2 1 0 0 5 1 0 1 1 2 2 0 2 0 0 2 0 3 0 2 1 3 1 2 1 2 2 3 2 0 2 0 0 1 0 2 1

Readme

Source
raw.​githubusercontent.​com

Verilog Automatic

This plugin can automatically add ports to the current editing file, generate module instances (need ctags),add instance connections ,add file header for verilog code. Both verilog-1995 and verilog-2001 style are supported. I borrowed the idea from automatic.vim which is a similar plugin for VIM, I just rewrote one for sublime text2&3.

Features


  • AutoPort
  • AutoInst
  • AutoDef
  • AddFileHeader

Description

AutoPort:(shift+f6)


Automatically add ports to the current editing file after the “/autoport/” mark.

  • NOTE: NOT SUPPORTED STYLE:

    input clk,output single_out,   //multiple input/output/inout keywords in the same line
    input clk,rst,
    chip_en;    //multiple signals separated by comma written in different lines
    
  • NOTE: Do not use this function when there are multiple modules in the same file.

Example:

Before

(verilog-1995 style):

module test(/*autoport*/);
    input [1:0]a;
    input b;
    output [2:0]c,d;
    inout e;

(verilog-2001 style):

module test(/*autoport*/);
    input wire[1:0]a;
    input wire b;
    output reg [2:0]c,d;
    inout wire e;

After:

module test(/*autoport*/
//inout
            e,
//output
            c,
            d,
//input
            a,
            b);

AutoInst:(shift+f7)


Automatically generate module instances after the “/autoinst/” mark (need ctags).

  • NOTE:Need to place the cursor on the module name, multiple-cursor supported to generate multiple instances.

Example:

Before:

test test_instance(/*autoinst*/);

After:

  • Place the cursor on the module name “test”

    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));
    

AutoDef:(shift+f8)


Automatically add instance connections after the /autodef/ mark.

Example:

before:

/*autodef*/



    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

after:

/*autodef*/
wire e;
wire [2:0]d;
wire c;
wire b;
wire [1:0]a;
//assign e=
//assign d=
//assign c=
//assign b=
//assign a=



test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

AddFileHeader:(shift+f9)


Add your personal information in the setting file(the user's setting file is better),like below or leave any of them empty:

{
        "Author":"Mike",
        "Company":"Microsoft",
        "Email":"whatever@yahoo.com"
    }

thus generates the file header like this:

//==================================================================================================
    //  Filename      : test.v
    //  Created On    : 2013-04-01 21:37:31
    //  Last Modified : 
    //  Revision      : 
    //  Author        : Mike
    //  Company       : Microsoft
    //  Email         : whatever@yahoo.com
    //
    //  Description   : 
    //
    //
    //==================================================================================================

Change log

05/08/2013

Add verilog-2001 style port declaration support.
Add comments support, single line commneted-out code will be ignored.