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Verilog Automatic

Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3

Details

  • 2013.08.06.08.11.47
  • github.​com
  • github.​com
  • 7 years ago
  • 49 minutes ago
  • 7 years ago

Installs

  • Total 15K
  • Win 10K
  • Mac 2K
  • Linux 3K
Jun 7 Jun 6 Jun 5 Jun 4 Jun 3 Jun 2 Jun 1 May 31 May 30 May 29 May 28 May 27 May 26 May 25 May 24 May 23 May 22 May 21 May 20 May 19 May 18 May 17 May 16 May 15 May 14 May 13 May 12 May 11 May 10 May 9 May 8 May 7 May 6 May 5 May 4 May 3 May 2 May 1 Apr 30 Apr 29 Apr 28 Apr 27 Apr 26 Apr 25 Apr 24 Apr 23
Windows 3 7 3 6 1 9 12 9 4 8 9 10 5 5 4 8 6 4 2 5 11 6 4 8 6 11 5 7 3 4 2 7 11 5 4 5 7 2 10 11 3 11 9 6 8 3
Mac 0 0 2 1 2 3 2 2 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 2 0 0 2 0 0 1 0 1 1 0 2 1 0 1 0 0 0 1
Linux 0 3 1 2 1 0 0 1 1 2 2 1 2 0 1 0 0 3 2 2 0 5 2 1 1 5 0 4 2 4 2 1 1 3 2 4 2 4 2 3 3 3 3 2 0 1

Readme

Source
raw.​githubusercontent.​com

Verilog Automatic

This plugin can automatically add ports to the current editing file, generate module instances (need ctags),add instance connections ,add file header for verilog code. Both verilog-1995 and verilog-2001 style are supported. I borrowed the idea from automatic.vim which is a similar plugin for VIM, I just rewrote one for sublime text2&3.

Features


  • AutoPort
  • AutoInst
  • AutoDef
  • AddFileHeader

Description

AutoPort:(shift+f6)


Automatically add ports to the current editing file after the “/autoport/” mark.

  • NOTE: NOT SUPPORTED STYLE:

    input clk,output single_out,   //multiple input/output/inout keywords in the same line
    input clk,rst,
    chip_en;    //multiple signals separated by comma written in different lines
    
  • NOTE: Do not use this function when there are multiple modules in the same file.

Example:

Before

(verilog-1995 style):

module test(/*autoport*/);
    input [1:0]a;
    input b;
    output [2:0]c,d;
    inout e;

(verilog-2001 style):

module test(/*autoport*/);
    input wire[1:0]a;
    input wire b;
    output reg [2:0]c,d;
    inout wire e;

After:

module test(/*autoport*/
//inout
            e,
//output
            c,
            d,
//input
            a,
            b);

AutoInst:(shift+f7)


Automatically generate module instances after the “/autoinst/” mark (need ctags).

  • NOTE:Need to place the cursor on the module name, multiple-cursor supported to generate multiple instances.

Example:

Before:

test test_instance(/*autoinst*/);

After:

  • Place the cursor on the module name “test”

    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));
    

AutoDef:(shift+f8)


Automatically add instance connections after the /autodef/ mark.

Example:

before:

/*autodef*/



    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

after:

/*autodef*/
wire e;
wire [2:0]d;
wire c;
wire b;
wire [1:0]a;
//assign e=
//assign d=
//assign c=
//assign b=
//assign a=



test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

AddFileHeader:(shift+f9)


Add your personal information in the setting file(the user's setting file is better),like below or leave any of them empty:

{
        "Author":"Mike",
        "Company":"Microsoft",
        "Email":"whatever@yahoo.com"
    }

thus generates the file header like this:

//==================================================================================================
    //  Filename      : test.v
    //  Created On    : 2013-04-01 21:37:31
    //  Last Modified : 
    //  Revision      : 
    //  Author        : Mike
    //  Company       : Microsoft
    //  Email         : whatever@yahoo.com
    //
    //  Description   : 
    //
    //
    //==================================================================================================

Change log

05/08/2013

Add verilog-2001 style port declaration support.
Add comments support, single line commneted-out code will be ignored.