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Verilog Automatic

Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3

Details

  • 2013.08.06.08.11.47
  • github.​com
  • github.​com
  • 7 years ago
  • 1 hour ago
  • 8 years ago

Installs

  • Total 16K
  • Win 11K
  • Mac 2K
  • Linux 3K
Oct 28 Oct 27 Oct 26 Oct 25 Oct 24 Oct 23 Oct 22 Oct 21 Oct 20 Oct 19 Oct 18 Oct 17 Oct 16 Oct 15 Oct 14 Oct 13 Oct 12 Oct 11 Oct 10 Oct 9 Oct 8 Oct 7 Oct 6 Oct 5 Oct 4 Oct 3 Oct 2 Oct 1 Sep 30 Sep 29 Sep 28 Sep 27 Sep 26 Sep 25 Sep 24 Sep 23 Sep 22 Sep 21 Sep 20 Sep 19 Sep 18 Sep 17 Sep 16 Sep 15 Sep 14 Sep 13
Windows 8 7 14 8 7 7 13 8 13 10 5 5 8 15 5 10 11 3 2 10 4 4 9 3 9 5 5 6 6 3 5 12 6 7 12 6 9 7 5 5 7 13 18 6 8 7
Mac 0 1 1 2 1 1 2 0 2 3 1 1 0 0 1 0 0 2 3 2 1 2 1 0 0 0 2 1 0 0 0 0 1 0 1 2 3 0 0 0 1 0 1 0 1 1
Linux 2 1 1 0 3 1 4 2 2 2 0 4 2 1 3 2 2 1 4 0 2 0 3 2 0 1 0 1 1 2 0 0 2 0 1 2 4 1 1 1 1 1 1 1 2 1

Readme

Source
raw.​githubusercontent.​com

Verilog Automatic

This plugin can automatically add ports to the current editing file, generate module instances (need ctags),add instance connections ,add file header for verilog code. Both verilog-1995 and verilog-2001 style are supported. I borrowed the idea from automatic.vim which is a similar plugin for VIM, I just rewrote one for sublime text2&3.

Features


  • AutoPort
  • AutoInst
  • AutoDef
  • AddFileHeader

Description

AutoPort:(shift+f6)


Automatically add ports to the current editing file after the “/autoport/” mark.

  • NOTE: NOT SUPPORTED STYLE:

    input clk,output single_out,   //multiple input/output/inout keywords in the same line
    input clk,rst,
    chip_en;    //multiple signals separated by comma written in different lines
    
  • NOTE: Do not use this function when there are multiple modules in the same file.

Example:

Before

(verilog-1995 style):

module test(/*autoport*/);
    input [1:0]a;
    input b;
    output [2:0]c,d;
    inout e;

(verilog-2001 style):

module test(/*autoport*/);
    input wire[1:0]a;
    input wire b;
    output reg [2:0]c,d;
    inout wire e;

After:

module test(/*autoport*/
//inout
            e,
//output
            c,
            d,
//input
            a,
            b);

AutoInst:(shift+f7)


Automatically generate module instances after the “/autoinst/” mark (need ctags).

  • NOTE:Need to place the cursor on the module name, multiple-cursor supported to generate multiple instances.

Example:

Before:

test test_instance(/*autoinst*/);

After:

  • Place the cursor on the module name “test”

    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));
    

AutoDef:(shift+f8)


Automatically add instance connections after the /autodef/ mark.

Example:

before:

/*autodef*/



    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

after:

/*autodef*/
wire e;
wire [2:0]d;
wire c;
wire b;
wire [1:0]a;
//assign e=
//assign d=
//assign c=
//assign b=
//assign a=



test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

AddFileHeader:(shift+f9)


Add your personal information in the setting file(the user's setting file is better),like below or leave any of them empty:

{
        "Author":"Mike",
        "Company":"Microsoft",
        "Email":"whatever@yahoo.com"
    }

thus generates the file header like this:

//==================================================================================================
    //  Filename      : test.v
    //  Created On    : 2013-04-01 21:37:31
    //  Last Modified : 
    //  Revision      : 
    //  Author        : Mike
    //  Company       : Microsoft
    //  Email         : whatever@yahoo.com
    //
    //  Description   : 
    //
    //
    //==================================================================================================

Change log

05/08/2013

Add verilog-2001 style port declaration support.
Add comments support, single line commneted-out code will be ignored.