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Verilog Automatic

by Tian-Changsong ALL Trending

Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3

Details

  • 2013.08.06.08.11.47
  • github.​com
  • github.​com
  • 9 years ago
  • 35 minutes ago
  • 9 years ago

Installs

  • Total 20K
  • Win 15K
  • Mac 2K
  • Linux 3K
Jul 5 Jul 4 Jul 3 Jul 2 Jul 1 Jun 30 Jun 29 Jun 28 Jun 27 Jun 26 Jun 25 Jun 24 Jun 23 Jun 22 Jun 21 Jun 20 Jun 19 Jun 18 Jun 17 Jun 16 Jun 15 Jun 14 Jun 13 Jun 12 Jun 11 Jun 10 Jun 9 Jun 8 Jun 7 Jun 6 Jun 5 Jun 4 Jun 3 Jun 2 Jun 1 May 31 May 30 May 29 May 28 May 27 May 26 May 25 May 24 May 23 May 22 May 21
Windows 3 15 6 5 10 8 9 6 11 4 2 6 9 11 12 7 3 3 4 5 4 9 6 3 4 4 10 8 12 5 3 5 3 6 6 5 6 5 4 5 7 11 11 13 6 9
Mac 0 0 1 0 0 3 0 0 1 0 0 0 0 0 1 0 0 1 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 4 0 1 0 1 0 0 0 0 0 0
Linux 1 5 0 0 1 2 0 1 0 4 0 2 2 2 2 1 0 0 0 1 0 0 3 1 1 2 0 1 1 4 1 1 1 1 1 1 2 0 1 1 0 0 3 2 1 0

Readme

Source
raw.​githubusercontent.​com

Verilog Automatic

This plugin can automatically add ports to the current editing file, generate module instances (need ctags),add instance connections ,add file header for verilog code. Both verilog-1995 and verilog-2001 style are supported. I borrowed the idea from automatic.vim which is a similar plugin for VIM, I just rewrote one for sublime text2&3.

Features


  • AutoPort
  • AutoInst
  • AutoDef
  • AddFileHeader

Description

AutoPort:(shift+f6)


Automatically add ports to the current editing file after the “/autoport/” mark.

  • NOTE: NOT SUPPORTED STYLE:

    input clk,output single_out,   //multiple input/output/inout keywords in the same line
    input clk,rst,
    chip_en;    //multiple signals separated by comma written in different lines
    
  • NOTE: Do not use this function when there are multiple modules in the same file.

Example:

Before

(verilog-1995 style):

module test(/*autoport*/);
    input [1:0]a;
    input b;
    output [2:0]c,d;
    inout e;

(verilog-2001 style):

module test(/*autoport*/);
    input wire[1:0]a;
    input wire b;
    output reg [2:0]c,d;
    inout wire e;

After:

module test(/*autoport*/
//inout
            e,
//output
            c,
            d,
//input
            a,
            b);

AutoInst:(shift+f7)


Automatically generate module instances after the “/autoinst/” mark (need ctags).

  • NOTE:Need to place the cursor on the module name, multiple-cursor supported to generate multiple instances.

Example:

Before:

test test_instance(/*autoinst*/);

After:

  • Place the cursor on the module name “test”

    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));
    

AutoDef:(shift+f8)


Automatically add instance connections after the /autodef/ mark.

Example:

before:

/*autodef*/



    test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

after:

/*autodef*/
wire e;
wire [2:0]d;
wire c;
wire b;
wire [1:0]a;
//assign e=
//assign d=
//assign c=
//assign b=
//assign a=



test test_instance(/*autoinst*/
            .e(e),
            .c(c),
            .d(d[2:0]),
            .a(a[1:0]),
            .b(b));

AddFileHeader:(shift+f9)


Add your personal information in the setting file(the user's setting file is better),like below or leave any of them empty:

{
        "Author":"Mike",
        "Company":"Microsoft",
        "Email":"whatever@yahoo.com"
    }

thus generates the file header like this:

//==================================================================================================
    //  Filename      : test.v
    //  Created On    : 2013-04-01 21:37:31
    //  Last Modified : 
    //  Revision      : 
    //  Author        : Mike
    //  Company       : Microsoft
    //  Email         : whatever@yahoo.com
    //
    //  Description   : 
    //
    //
    //==================================================================================================

Change log

05/08/2013

Add verilog-2001 style port declaration support.
Add comments support, single line commneted-out code will be ignored.