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by bootsiaz ST3

A VHDL and Verilog IDE for Sublime Text 3.



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  • Win 548
  • OS X 133
  • Linux 210
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Linux 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0



HDLProject is a Verilog and VHDL IDE for Sublime Text 3.


  • Simplify project creation
  • Side-by-side hierarchy and file system
  • Automated syntax checking
  • On-hover popups for any definition
  • Accelerated project navigation
  • Multitask with multiple windows/projects
  • Build integration with Vivado and Quartus
  • Code on Windows/Linux/macOS
  • License is not node-locked or time-limited






Project Creation

Creating a Hierarchical Project from a .sublime-project File

A simple method of project creation is by sourcing a reference ST3 project. This ST3 .sublime-project can be easily created by opening a new view, adding folders to the project via the project menu, and saving the .sublime-project file. You can then create a HDLProject project via the command palette (ctrl+shift+p) using the Create HDL Project command, and selecting current project in the drop-down menu. This will create and open a new HDLProject project and write a new entry to the package settings file.

Note that when adding folders to your reference ST3 project, all VHDL and Verilog files will be parsed. For best performance, only include folders that are required for your design. In the reference .sublime-project file, folder_exclude_patterns and file_exclude_patterns lists are supported (although using wildcards is not).

If the window opens without the sidebar visible, you can select View->Side Bar->Show Side Bar

Once the hierarchical project is created, the status bar will indicate if there are any ambiguous files – multiple HDL files with the same module/entity name. These can be cleaned up by running the Cleanup Module Ambiguity command from the command palette. The ambiguous modules are displayed in a drop-down list, and the user can select which path they want to keep in the project, the remaining paths will be removed. The reference .sublime-project will be automatically updated with new file_exclude_patterns.

Creating a Hierarchical Project from a Vivado or Quartus Project File

Alternatively, if using Vivado or Quartus, it makes sense to keep your HDLProject project in sync with your designs. There are a couple ways of doing this. The simplest method is to source your Vivado .xpr or Quartus .qsf. Enter the path of your vendor project file in the files_l list in the HDLProject settings file.

You can also source a project Tcl. First, create a project Tcl in the vendor gui. Then reference this in the files_l list. If using Vivado, make sure to select “write all project properties” when generating the Tcl. (A tcl script is also included to create the project tcl for Vivado.)

Creating a Hierarchical Project from a List of Files and Folders

A third way of creating a project is to add the folders and files directly into the lists in the HDLProject package settings file. This is useful when working with well organized libraries or smaller designs.

The package settings file supports an unlimited number of project configurations.

Use the Refresh HDL Project command to update the active project in memory.

Navigating the Project

The created directory structure is a tree of symlinked files and is stored at your custom output path provided in the preferences file. If not defined, it will be created at $TEMP/sublime_hdl_project on Windows, or ~/.sublime_hdl_project on macOS and Linux.

The created project is separated into a 'hierarchy' and 'libraries' directories. The 'hierarchy' contains the hierarchical RTL. The 'libraries' contains the original source folders. You can quickly jump between a file in the hierarchy to its source folder by using the sidebar Reveal in Sidebar File System and Reveal in Sidebar Hierarchy commands, accessed from the context menu when right-clicking on a file in the sidebar.

Building FPGA

HDLProject integrates with the Vivado and Quartus Tcl command line. You can create your own scripts and add their paths to the build_tcl list in the preferences file. These scripts can then be run from the command palette via the HDLProject: Build Tcl command. Note that Tcl scripts can only be run after a project has been created. Some example Tcl scripts are provided with the plugin to help get you started.

Builds can be cancelled at any time. Any succeeding build will cancel any build that is currently running. HDLProject includes a process manager object that will keep track of, and later terminate, any spawned processes when cancelling a build or closing ST3. This allows for complex tasks like building an entire FPGA project, opening the GUI, analyzing placement and routing, all from a tcl script, and initiated from ST3.

The following parameters are passed to the tcl scripts:

  • arg0: project_file setting from the preferences file for the active project
  • arg1: top_module setting from the preferences file for the active project
  • arg2: The file name of the open view window.active_view().file_name()
  • arg3: User defined string user_tcl_arg

On-Hover Definitions

Once the project is in memory, a popup will appear when hovering for a few seconds over any port, signal, reg, wire, constant, generic, parameter, define, localparam, instance, variable, type, subtype, use package or include statement. This can be disabled with ctrl+shift+l (cmd+shift+l in macOS).

Popups allow for quick navigation within the active file and project. For example, hovering over a signal will provide information on its definition as well as a link to the definition. Links to assignments (fan-in) within the file are also provided.

Navigation links are also provided when hovering over a module instance or package/incude statement, which provides a file preview and the ability to jump to any line in that file.

Syntax Checking

Syntax checking requires a FPGA tool installation and the location specified with the syntax_tool_path setting. If not defined, it will try using the build_tool_path. Vivado and Quartus are currently supported. The check_syntax_on_save setting will call the syntax checker thread when any file is saved within a HDL Project window.

The number of errors is displayed in the status bar. You can navigate syntax errors in your project by using the go_to_prev_syntax_error and go_to_next_syntax_error commands. A dot is placed in the gutter to the left of the line associated with any error. Hovering over the dot will provide a popup with the error message from the syntax log. To view the syntax log, enable the check_syntax_panel setting. Note, as with most other tools, syntax checking only works within an active project.

Retrieving Compile Order

To get a list of files in the right compile order, run the Create Compile Order command from the command palette. If a file you need is missing from the project, for example a non-HDL file, you can specify it in the 'libraries' section in the project settings.

Key Mapping

Windows and Linux:

{ "keys": ["ctrl+shift+l"], "command": "toggle_hdl_popups" },
{ "keys": ["ctrl+shift+b"], "command": "cancel_tcl_build"},


{ "keys": ["super+shift+l"], "command": "toggle_hdl_popups" },
{ "keys": ["super+shift+b"], "command": "cancel_tcl_build" },

Command Reference

The following is a list of HDLProject commands accessible from the Command Palette (ctrl+shift+p). Any one of these commands can be mapped to keys via the Preferences->Key Bindings file.

  • open_hdl_project
  • delete_hdl_project
  • refresh_hdl_project
  • context_open_original_containing_folder
  • open_hdl_project_file
  • do_tcl_build
  • toggle_hdl_popups
  • create_hdl_project
  • generate_hdl_compile_order
  • check_hdl_syntax
  • go_to_prev_hdl_syntax_error
  • go_to_next_hdl_syntax_error
  • cleanup_module_ambiguity
  • open_reference_project
  • comment_selection
  • cancel_tcl_build
  • open_hdl_panel
  • open_module_by_filename
  • open_module_by_hierarchy
  • generate_file_list
  • open_output_path
  • explore_file_system_in_quick_panel
  • add_new_project_entry


VHDL and Verilog completions for common keywords is included. These are still under development.


  • Tested on Windows 10, Ubuntu 16.04, and macOS High Sierra

Syntax Highlighting

HDLProject comes with forked versions of the sublime-vhdl and sublime-verilog syntax highlighting packages. These can be selected from the View menu, at View->Syntax->HDLProject->VHDL/Verilog.

These updated syntaxes allow for uncluttered navigation of the active file and project. Typing ctrl+R brings up the Goto Definition dropdown for the active file. This allows you to jump to module instances within that file. Typing ctrl+shift+R bring up the Goto Definition dropdown for the project. This allows you to jump to any module/entity definition in the project.

The packages remain open source. If interested, they can also be found externally here: * VHDL Syntax Package * Verilog Syntax Package


Since ST3 syntax only supports single-line regex matching, the Goto Panel and color scheme will pickup Verilog instances in only the specified format. For instances without parameters include the opening bracket on the first line.

instance_name module_name (

For instances with parameters, the following is supported.

instance_name (
) module_name (

Note, the theme Boxy Theme was used for testing changes to the syntax files.

HDLProject on Windows

Admin Privileges

Note that on Windows, for advanced users, it is recommended to run ST3 with admin privileges. This allows for the creation of symlinks and speeds up project creation. Without admin privileges, hardlinks are created which are usually not supported by other plugins – for example, revision control plugins. Although HDLProject itself will work just fine.

Network Drives

For a project that contains files on a network drive, you need to be running ST3 in admin mode and have the EnableLinkedConnections registry key set to “1”. https://serverfault.com/questions/780639/enablelinkedconnections-isnt-working-on-some-windows-10-machines

Case Sensitivity

Files and folders are cases sensitive on all platforms.

Windows Path Character Limit

For hierarchies with paths longer than 260 characters (MAX_PATH), the Windows character limit will be exceeded. This may happen with large projects and/or when unwrapping IP cores. When the Windows MAX_PATH length is exceeded, the tool will automatically create secondary hierarchy folders with appropriate naming. If this becomes an issue, it is recommended the user shrink the entity/module or IP names to as few characters as possible.

Symbolic Link Limit

On Windows, there is also a maximum number of symbolic links that can be created. This will only be reached after a very large number of projects have been created, after several months, or years, depending on usage. Therefore, it is recommended to periodically cleanout old HDLProject directories.

Default Settings

  // Vivado or Quartus Tcl scripts.
  // Add your own scripts to this list.

  // Syntax checking requires Vivado installation and syntax_tool_path setting. 
  "check_syntax_on_save": true,    
  // Open and print stdout to a panel when checking syntax.    
  "check_syntax_panel": false,    

  // The email associated with a purchased license.
  "email": "",

  // If not defined, it will be created at $TEMP/sublime_hdl_project on 
  // Windows, or ~/.sublime_hdl_project on macOS and Linux. 
  // Cannot be a network drive on Windows. 
  "output_path": "",

  // Product key provided when purchasing. 
  "product_key": "",

  // A list of VHDL/Verilog projects
      // FPGA vendor tool path, indicate the full path to the bin folder
      "build_tool_path": "C:/Xilinx/Vivado/2017.2/bin",

      // A reference .sublime-project file
      // or a list of zero or more files (absolute paths)
      // or a Vivado or Quartus project (xpr, .qsf), or project Tcl

      // A list of zero or more folders where the project files reside.

      // ID sets the basename of the output folder and the tag in the project menu
      "id": "a10_soc",

      // Path to a FPGA project file. Vivado xpr or Quartus qsf.
      "fpga_project_file": "",

      // FPGA tool for syntax checking. If not defined, will use build_tool_path. Supported tools: Vivado
      "syntax_tool_path": "C:/Xilinx/Vivado/2017.2/bin",

      // Top level module/entity name
      // If not defined, it will automatically pick one. 
      "top_module": "ghrd_10as066n2_top",

      //If using vivado IP, indicate if you want to unwrap the hierarchy
      "unwrap_vivado_ip": false,

      "build_tool_path": "D:/intelFPGA_lite/17.1/quartus/bin64",
      "id": "cpu",
      "fpga_project_file": "C:/temp/cpu.qsf",
      "syntax_tool_path": "C:/Xilinx/Vivado/2017.2/bin",
      "top_module": "top"

      "build_tool_path": "C:/Xilinx/Vivado/2017.2/bin",
      "id": "cv_soc",
      "fpga_project_file": "",
      "syntax_tool_path": "C:/Xilinx/Vivado/2017.2/bin",
      //"top_module": ""

      "build_tool_path": "C:/Xilinx/Vivado/2017.2/bin",
      "id": "fpu_double",
      "fpga_project_file": "",
      "syntax_tool_path": "C:/Xilinx/Vivado/2017.2/bin",
      //"top_module": ""


  // Indicate whether the open hdl file will be automatically revealed in the sidebar. 
  "sync_sidebar": true,

  // Use this to pass in any string to a custom Tcl script.
  "user_tcl_arg": ""


HDLProject requires a license, but is currently free to try out. The license is not node-locked nor time-limited. Licenses are valid for a single person, on any number of machines, and are valid for all upgrades to the major version purchased. Please note, we reserve the right to end the free trial at any time. A license can be purchased at https://hdlproject.com.

Direct link: https://www.paypal.com/webapps/shoppingcart?flowlogging_id=f4c836486a29&mfid=1526876257539_f4c836486a29#/checkout/openButton

Please contact sales@intrachip.com with any questions or concerns.


HDLProject is usually installed as a plugin via Package Control within Sublime Text 3. Use shift+ctrl+P, type 'install', then type 'HDLProject' and press Enter.

Alternatively, you can clone the HDLProject repository from Bitbucket and copy to Sublime Text 3 'Packages' folder. In this case, you would copy the entire repository into a 'HDLProject' subfolder in the 'Packages' folder. You can easily find the Packages folder by selecting Preferences->Browse Packages.


Please contact us at info@intrachip.com and let us know what you think!



  • Added support for parsing Vivado .xpr and Quartus .qsf files.
  • Improved support for Verilog signal popups
  • Added initial Verilog completions
  • Added initial support for Quartus syntax checking
  • Tweaked VHDL and Verilog syntax.
  • Changed file name in hierarchy to reflect real file name instead of module name.
  • Tcl build panel name is now “build_tcl” instead of “exec”
  • Added ability to create a new project entry from the command pallette (Add New Project Entry) (Requires Sublime Text 3.1 or later)
  • Added commands for getting license and accessing website
  • Bug fixes


  • Fix for not resolving generics in verilog when generic is defined in ancestor module definition.
  • Fix for instance popup when capture has comments.
  • Fix for error due to race condition when closing window


  • Restructured HDL_Project object for data persistence using 'pickle'.
  • Existing projects will now automatically load from a binary .pkl file instead of having to recreate the entire object every time they are opened.


  • Improved support for working with files from network drives on Windows.
  • Added new commands: Open HDL Panel, Open Module by Filename, Open Module by Hierarchy, Open Output Path, Generate File List, Delete Project, Explore File System In Quick Panel
  • Updated Open HDL Project command to use the quick panel instead of opening platform's file explorer.
  • Refactored Threads module and project creation.
  • Bug fix for creating empty symlinked dirs outside output_path directory.
  • Added cancelling of active Tcl build when refresh project command is run.
  • Added initial symlinking of non-RTL folders if specified in folders list setting.
  • Various minor bug fixes.
  • Deprecated show_source_path setting.


  • Updated for full support on macOS
  • Added assignments to signal popups for Verilog
  • Fix for parsing erros when saving a few times quickly in succession.
  • Added syntax_tool_path setting


  • Updated signal popup formatting
  • Added support for VHDL variable, type, subtype, and record popups
  • Added local signal assignments to VHDL signal popups
  • Added support for generic popups when the generics have no default value.
  • Fixes for generic popups in multi-entity files.
  • Popup navigation is now context based
  • Fix for refresh_project using new timestamp
  • Minor stability fixes


  • Added forked and modded sublime-vhdl and sublime-verilog packages
  • Added support for alternate vhdl and verilog file extensions: .vhdl, .vho, .vht, .sv, .svh
  • Bugfix for generic parser for vhdl testbenches
  • Other stability fixes


  • Fixes for generic/parameter popups
  • Added secondary hierarchy folder creation on Windows when the 260 character path limit is exceeded.


  • Initial licensed beta version
  • Created website at https://hdlproject.com
  • Package setting “project_file” is now “fpga_project_file”
  • Added package setting “user_tcl_arg”
  • Added new commands: InstancePopoupEventListenerCommand, CommentSelectionCommand, GenericPopupEventListenerCommand
  • Added instance, use package, and include statement file preview popups.
  • Various fixes for popups in verilog
  • Added constant definition popups to verilog
  • Added generic/parameter popups with value resolving based on hierarchy.
  • Added support for multiple signal/reg/wire declarations on the same line.
  • Various stability fixes
  • Fixed recursive issue with refresh project command
  • Open reference project now opens the ST3 project in a new window
  • Reference ST3 project can now have partial paths.
  • .xci parsing now uses xml parser
  • Fixed all issues related to running in non-admin mode on Windows
  • Can now create HDLProject directly from reference ST3 project, settings file is auto-updated
  • Added license check and status

Copyright 2018, IntraChip Solutions Inc., All rights reserved.