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by Andrew Carter ST3

A Verilog and VHDL IDE for Sublime Text 3

Labels vhdl, verilog, fpga



  • Total 2K
  • Win 1K
  • Mac 210
  • Linux 373
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HDLProject is a Verilog and VHDL IDE for Sublime Text 3.


  • Simplify project creation
  • Side-by-side hierarchy and file system
  • Automated syntax checking
  • On-hover popups for any definition
  • Accelerated project navigation
  • Multitask with multiple windows/projects
  • Build integration with Vivado and Quartus
  • Code on Windows/Linux/macOS
  • License is not node-locked or time-limited


HDLProject is free to try out, but the user must get a license for regular use. If you like the plugin, please purchase at www.hdlproject.com and a product key will be emailed to you within 24 hours.

Please contact me at info@intrachip.com with any questions or concerns.






Project Creation

Creating a Hierarchical Project from a .sublime-project File

A simple method of project creation is by sourcing a reference ST3 project. This ST3 .sublime-project can be easily created by opening a new view, adding folders to the project via the project menu, and saving the .sublime-project file. You can then create a HDLProject project via the command palette (ctrl+shift+p) using the Create HDL Project command, and selecting current project in the drop-down menu. This will create and open a new HDLProject project and write a new entry to the package settings file.

Note that when adding folders to your reference ST3 project, all VHDL and Verilog files will be parsed. For best performance, only include folders that are required for your design. In the reference .sublime-project file, folder_exclude_patterns and file_exclude_patterns lists are supported. Wilcards for folder_exclude_patterns can be used in a limited way. For example, '*src' will ignore all files with the string 'src' in its path. Please consult the ST3 projects docs for usage. https://www.sublimetext.com/docs/3/projects.html

If the window opens without the sidebar visible, you can select View->Side Bar->Show Side Bar

Once the hierarchical project is created, the status bar will indicate if there are any ambiguous files – multiple HDL files with the same module/entity name. These can be cleaned up by running the Cleanup Module Ambiguity command from the command palette. The ambiguous modules are displayed in a drop-down list, and the user can select which path they want to keep in the project, the remaining paths will be removed. The reference .sublime-project will be automatically updated with new file_exclude_patterns.

Creating a Hierarchical Project from a Vivado or Quartus Project File

Alternatively, if using Vivado or Quartus, it makes sense to keep your HDLProject project in sync with your designs. There are a couple ways of doing this. The simplest method is to source your Vivado .xpr or Quartus .qsf. Enter the path of your vendor project file in the files_l list in the HDLProject settings file.

You can also source a project Tcl. First, create a project Tcl in the vendor gui. Then reference this in the files_l list. If using Vivado, make sure to select “write all project properties” when generating the Tcl. (A tcl script is also included to create the project tcl for Vivado.)

Creating a Hierarchical Project from a List of Files and Folders

A third way of creating a project is to add the folders and files directly into the lists in the HDLProject package settings file. This is useful when working with well organized libraries or smaller designs.

The package settings file supports an unlimited number of project configurations.

Use the Refresh HDL Project command to update the active project in memory.

Navigating the Project

The created directory structure is a tree of symlinked files and is stored at your custom output path provided in the preferences file. If not defined, it will be created at $TEMP/sublime_hdl_project on Windows, or ~/.sublime_hdl_project on macOS and Linux.

The created project is separated into a 'hierarchy' and 'libraries' directories. The 'hierarchy' contains the hierarchical RTL. The 'libraries' contains the original source folders. You can quickly jump between a file in the hierarchy to its source folder by using the sidebar Reveal in Sidebar File System and Reveal in Sidebar Hierarchy commands, accessed from the context menu when right-clicking on a file in the sidebar.

Building FPGA

HDLProject integrates with the Vivado and Quartus Tcl command line. You can create your own scripts and add their paths to the build_tcl list in the preferences file. These scripts can then be run from the command palette via the HDLProject: Build Tcl command. Note that Tcl scripts can only be run after a project has been created. Some example Tcl scripts are provided with the plugin to help get you started.

Builds can be cancelled at any time. Any succeeding build will cancel any build that is currently running. HDLProject includes a process manager object that will keep track of, and later terminate, any spawned processes when cancelling a build or closing ST3. This allows for complex tasks like building an entire FPGA project, opening the GUI, analyzing placement and routing, all from a tcl script, and initiated from ST3.

The following parameters are passed to the tcl scripts:

  • arg0: project_file setting from the preferences file for the active project
  • arg1: top_module setting from the preferences file for the active project
  • arg2: The file name of the open view window.active_view().file_name()
  • arg3: User defined string user_tcl_arg

On-Hover Definitions

Once the project is in memory, a popup will appear when hovering for a few seconds over any port, signal, reg, wire, constant, generic, parameter, define, localparam, instance, variable, type, subtype, use package or include statement. This can be disabled with ctrl+shift+l (cmd+shift+l in macOS).

Popups allow for quick navigation within the active file and project. For example, hovering over a signal will provide information on its definition as well as a link to the definition. Links to assignments (fan-in) within the file are also provided.

Navigation links are also provided when hovering over a module instance or package/incude statement, which provides a file preview and the ability to jump to any line in that file.

Syntax Checking

Syntax checking requires a FPGA tool installation and the location specified with the syntax_tool_path setting. If not defined, it will try using the build_tool_path. Vivado and Quartus are currently supported. The check_syntax_on_save setting will call the syntax checker thread when any file is saved within a HDL Project window.

The number of errors is displayed in the status bar. You can navigate syntax errors in your project by using the go_to_prev_syntax_error and go_to_next_syntax_error commands. A dot is placed in the gutter to the left of the line associated with any error. Hovering over the dot will provide a popup with the error message from the syntax log. To view the syntax log, enable the check_syntax_panel setting. Note, as with most other tools, syntax checking only works within an active project.

Retrieving Compile Order

To get a list of files in the right compile order, run the Create Compile Order command from the command palette. If a file you need is missing from the project, for example a non-HDL file, you can specify it in the 'libraries' section in the project settings.

Key Mapping

Windows and Linux:

{ "keys": ["ctrl+shift+l"], "command": "toggle_hdl_popups" },
{ "keys": ["ctrl+shift+b"], "command": "cancel_tcl_build"},


{ "keys": ["super+shift+l"], "command": "toggle_hdl_popups" },
{ "keys": ["super+shift+b"], "command": "cancel_tcl_build" },

Command Reference

The following is a list of HDLProject commands accessible from the Command Palette (ctrl+shift+p). Any one of these commands can be mapped to keys via the Preferences->Key Bindings file.

  • open_hdl_project
  • delete_hdl_project
  • refresh_hdl_project
  • context_open_original_containing_folder
  • open_hdl_project_file
  • do_tcl_build
  • toggle_hdl_popups
  • create_hdl_project
  • generate_hdl_compile_order
  • check_hdl_syntax
  • go_to_prev_hdl_syntax_error
  • go_to_next_hdl_syntax_error
  • cleanup_module_ambiguity
  • open_reference_project
  • comment_selection
  • cancel_tcl_build
  • open_hdl_panel
  • open_module_by_filename
  • open_module_by_hierarchy
  • generate_file_list
  • open_output_path
  • explore_file_system_in_quick_panel
  • add_new_project_entry
  • open_hdl_parent
  • create_data_structure_json
  • update_project_generics


VHDL and Verilog completions for common keywords is included. These are still under development.


  • Tested on Windows 10, Ubuntu 16.04, and macOS High Sierra

Syntax Highlighting

HDLProject comes with forked versions of the sublime-vhdl and sublime-verilog syntax highlighting packages. These can be selected from the View menu, at View->Syntax->HDLProject->VHDL/Verilog.

These updated syntaxes allow for uncluttered navigation of the active file and project. Typing ctrl+R brings up the Goto Definition dropdown for the active file. This allows you to jump to module instances within that file. Typing ctrl+shift+R bring up the Goto Definition dropdown for the project. This allows you to jump to any module/entity definition in the project.

The packages remain open source. If interested, they can also be found externally here: * VHDL Syntax Package * Verilog Syntax Package


Since ST3 syntax only supports single-line regex matching, the Goto Panel and color scheme will pickup Verilog instances in only the specified format. For instances without parameters include the opening bracket on the first line.

instance_name module_name (

For instances with parameters, the following is supported.

instance_name (
) module_name (

Note, the theme Boxy Theme was used for testing changes to the syntax files.

HDLProject on Windows

Admin Privileges

Note that on Windows, for advanced users, it is recommended to run ST3 with admin privileges. This allows for the creation of symlinks and speeds up project creation. Without admin privileges, hardlinks are created which are usually not supported by other plugins – for example, revision control plugins. Although HDLProject itself will work just fine.

Network Drives

For a project that contains files on a network drive, you need to be running ST3 in admin mode and have the EnableLinkedConnections registry key set to “1”. https://serverfault.com/questions/780639/enablelinkedconnections-isnt-working-on-some-windows-10-machines

Case Sensitivity

Files and folders are cases sensitive on all platforms.

Windows Path Character Limit

For hierarchies with paths longer than 260 characters (MAX_PATH), the Windows character limit will be exceeded. This may happen with large projects and/or when unwrapping IP cores. When the Windows MAX_PATH length is exceeded, the tool will automatically create secondary hierarchy folders with appropriate naming. If this becomes an issue, it is recommended the user shrink the entity/module or IP names to as few characters as possible.

Symbolic Link Limit

On Windows, there is also a maximum number of symbolic links that can be created. This will only be reached after a very large number of projects have been created, after several months, or years, depending on usage. Therefore, it is recommended to periodically cleanout old HDLProject directories.

Default Settings

  // Vivado or Quartus Tcl scripts.
  // Add your own scripts to this list.

  // Global FPGA vendor tool path, indicate the full path to the bin folder
  "build_tool_path": "C:/Xilinx/Vivado/2017.2/bin",

  // Syntax checking requires Vivado installation and syntax_tool_path setting. 
  "check_syntax_on_save": true,    
  // Open and print stdout to a panel when checking syntax.    
  "check_syntax_panel": false,    

  // Select to show syntax check error messages from third party tools below the line they reference.
  // A dot in the gutter with a popup error message is always available. 
  "check_syntax_phantoms": true,

  // The email associated with a purchased license.
  "email": "",

  // Create expanded hierarchy for path lengths beyond Windows limit of 260 chars
  "expand_hierarchy_on_win_path_limit": true,

  // Extend completions to all files in scope. For example, package or header files. 
  "extend_completions": true,

  // If not defined, it will be created at $TEMP/sublime_hdl_project on 
  // Windows, or ~/.sublime_hdl_project on macOS and Linux. 
  // Cannot be a network drive on Windows. 
  "output_path": "",

  // Parse the fpga_project_file when creating project.
  "parse_fpga_project_file": true,

  // Parse all HDL files for generics and parameters during project creation and refresh
  "parse_generics_and_parameters": true,

  // Enable/disable popups in VHDL and Verilog files
  "popups_enabled": true,

  // Check syntax automatically after refreshing a project
  "post_refresh_check_syntax": false,

  // Product key provided when purchasing. 
  "product_key": "",

  // A list of VHDL/Verilog projects
      // FPGA vendor tool path, indicate the full path to the bin folder
      "build_tool_path": "C:/Xilinx/Vivado/2017.2/bin",

      // A reference .sublime-project file
      // or a list of zero or more files (absolute paths)
      // or a Vivado or Quartus project (xpr, .qsf), or project Tcl

      // A list of zero or more folders where the project files reside.

      // ID sets the basename of the output folder and the tag in the project menu
      "id": "a10_soc",

      // Path to a FPGA project file. Vivado xpr or Quartus qsf.
      "fpga_project_file": "",

      // FPGA tool for syntax checking. If not defined, will use build_tool_path. Supported tools: Vivado
      "syntax_tool_path": "C:/Xilinx/Vivado/2017.2/bin",

      // Top level module/entity name
      // If not defined, it will automatically pick one. 
      "top_module": "ghrd_10as066n2_top",

      //If using vivado IP, indicate if you want to unwrap the hierarchy
      "unwrap_vivado_ip": false,

      "build_tool_path": "D:/intelFPGA_lite/17.1/quartus/bin64",
      "id": "cpu",
      "fpga_project_file": "C:/temp/cpu.qsf",
      "syntax_tool_path": "C:/Xilinx/Vivado/2017.2/bin",
      "top_module": "top"

      "build_tool_path": "C:/Xilinx/Vivado/2017.2/bin",
      "id": "cv_soc",
      "fpga_project_file": "",
      "syntax_tool_path": "C:/Xilinx/Vivado/2017.2/bin",
      //"top_module": ""

    // Example simplified project settings
      "id": "fpu_double",
      "syntax_tool_path": "C:/Xilinx/Vivado/2017.2/bin",

      "fpga_project_file": "C:/temp/cpu.xpr",
      "id": "cpu_b",
      "syntax_tool_path": "C:/Xilinx/Vivado/2017.2/bin",


  // Open and print stdout to a panel when refreshing the project.
  "refresh_project_panel": true,

  // When clicking popup links, navigate within a separate horizontal panel above the active view.
  "split_panel_mode": false,

  // Indicate whether the open hdl file will be automatically revealed in the sidebar. 
  "sync_sidebar": true,

  // Use this to pass in any string to a custom Tcl script.
  "user_tcl_arg": "",

  // A list of projects grouped into workspaces.
      "id": "my_ws",
      "id": "my_ws_b",



HDLProject requires a license for regular use. The license is not node-locked nor time-limited. Licenses are valid for a single person, on any number of machines, and are valid for all upgrades to the major version purchased. A license can be purchased at https://hdlproject.com.

Please contact me at info@intrachip.com with any questions or concerns.


HDLProject is usually installed as a plugin via Package Control within Sublime Text 3. Use shift+ctrl+P, type 'install', then type 'HDLProject' and press Enter.


Please contact me at info@intrachip.com with any questions or concerns.



  • Added support for extending completions to all files in scope.
  • Added new boolean setting “extend_completions”.
  • Added syntax support for 'localparam integer' and 'localparam int'
  • Added initial support for creating workspaces, though can't do anything with them yet.
  • Sped up project creation and refresh, especially on Linux.
  • Deprecated “post_refresh_update_generics” setting.
  • Added “parse_generics_and_parameters” setting.
  • Added limited support to wildcards in folder_exclude_patterns
  • Bug fixes.


  • Added initial support for popups in standalone VHDL and Verilog files
  • Added popups_enabled setting
  • Added post_refresh_check_syntax setting
  • Added post_refresh_update_generics setting
  • Added expand_hierarchy_on_win_path_limit setting for Windows
  • Bugfix to detect moved source files during refresh project
  • Bugfix for records not being picked up in signal assignment list
  • Fix for popup link line numbers


  • Bugfix for no common drive letter on Windows.


  • Verilog regex speedup
  • Project refresh is now more intelligent and does not require recreating entire project.
  • x3 speedup for large projects when creating or refreshing a project.
  • Added pre_parse_script option for running custom commands before project creation and refresh.
  • Added split_panel_mode option and command for working with clones of the same file in different panels.
  • Added auto-split-panel when selecting signal links to the same file.
  • Fix for open-parent-module and instance links due to path case.
  • Fix for finding Verilog instance with positional parameters.

Copyright 2019, IntraChip Solutions Inc., All rights reserved.