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Smart VHDL

by TheClams ST3

Syntax Highlighting, Snippets, code navigation and more for VHDL

Details

Installs

  • Total 2K
  • Win 1K
  • OS X 191
  • Linux 403
Feb 25 Feb 24 Feb 23 Feb 22 Feb 21 Feb 20 Feb 19 Feb 18 Feb 17 Feb 16 Feb 15 Feb 14 Feb 13 Feb 12 Feb 11 Feb 10 Feb 9 Feb 8 Feb 7 Feb 6 Feb 5 Feb 4 Feb 3 Feb 2 Feb 1 Jan 31 Jan 30 Jan 29 Jan 28 Jan 27 Jan 26 Jan 25 Jan 24 Jan 23 Jan 22 Jan 21 Jan 20 Jan 19 Jan 18 Jan 17 Jan 16 Jan 15 Jan 14 Jan 13 Jan 12 Jan 11
Windows 0 4 4 5 4 4 4 3 1 2 3 8 5 4 1 1 1 5 3 5 6 4 0 5 5 7 7 4 3 5 3 6 3 10 7 2 6 1 7 4 8 3 3 6 4 3
OS X 1 1 2 1 0 0 1 1 1 1 0 3 0 2 1 0 1 3 0 3 0 0 0 0 0 0 0 0 1 0 1 2 1 2 1 0 0 0 1 1 3 3 1 0 0 1
Linux 0 0 4 3 1 4 2 0 0 4 10 1 1 2 0 5 1 5 7 1 1 1 3 7 1 1 1 4 1 4 1 5 1 0 2 0 1 1 4 3 6 4 0 0 2 2

Readme

Source
raw.​githubusercontent.​com

Sublime Text 'Smart' VHDL Package

General

The goal of this plugin is to provide IDE-like features for VHDL (similar to my other plugin for SystemVerilog) :

Compare to the basic VHDL plugin it already proposes:

  • a proper symbol definition for easy code navigation
  • Some basic indentation definition
  • A complete set of snippets written by https://github.com/ccornish
  • Tooltip to get signal definition on mouse hover
  • Generate a design hierarchy (list of every sub-block) (available in the command panel)

Future features includes code completion (for record, enum, …), code alignement, block instantiation, …

Description

Syntax Highlighting:

Syntax highlighting is based on the VHDL bundle for Textmate, with a rework of scope to be aligned with the SystemVerilog plugin and some support of VHDL2008 features

Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://bitbucket.org/Clams/sublimesystemverilog/downloads/Sunburst2.tmTheme

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Show hierarchy of a block (all its sub-block and their sub-block)

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection

Code Alignement:

  • Align module instantiation

Configuration

To see all existing configuration option, go to Preferences->Package Settings->SmartVHDL->Settings (Default).

To edit settings open the Settings (User), and add parameter with the value you want.

Keymapping example

To map key to the different feature, simply add the following to your user .sublime-keymap file:

{
        "keys": ["ctrl+f10"], "command": "vhdl_module_inst",
        "context":
        [
            { "key": "num_selections", "operator": "equal", "operand": 1 },
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["ctrl+shift+a"], "command": "vhdl_align",
        "context":
        [
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["f12"], "command": "vhdl_hierarchy_goto_definition",
        "context":[
            { "key": "selector", "operator": "equal", "operand": "text.result-vhdl"}
        ]
    }