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Smart VHDL

by TheClams ST3

Syntax Highlighting, Snippets, code navigation and more for VHDL

Details

Installs

  • Total 616
  • Win 404
  • OS X 62
  • Linux 150
Sep 20 Sep 19 Sep 18 Sep 17 Sep 16 Sep 15 Sep 14 Sep 13 Sep 12 Sep 11 Sep 10 Sep 9 Sep 8 Sep 7 Sep 6 Sep 5 Sep 4 Sep 3 Sep 2 Sep 1 Aug 31 Aug 30 Aug 29 Aug 28 Aug 27 Aug 26 Aug 25 Aug 24 Aug 23 Aug 22 Aug 21 Aug 20 Aug 19 Aug 18 Aug 17 Aug 16 Aug 15 Aug 14 Aug 13 Aug 12 Aug 11 Aug 10 Aug 9 Aug 8 Aug 7 Aug 6
Windows 2 5 6 6 3 10 8 21 6 5 3 4 3 3 3 5 2 3 1 1 6 4 3 2 4 2 7 4 5 5 4 4 1 3 4 5 9 2 2 3 2 5 11 5 1 3
OS X 2 0 4 0 0 0 1 1 3 0 0 1 1 0 3 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 3 1 0 2 1 0 0 0 0 0 1 0 0 0
Linux 0 3 4 0 1 1 7 3 3 3 1 0 2 3 1 6 2 1 1 5 3 1 0 0 2 1 2 5 3 1 1 2 0 2 3 3 1 0 0 3 2 0 3 0 2 0

Readme

Source
raw.​githubusercontent.​com

Sublime Text 'Smart' VHDL Package

General

The goal of this plugin is to provide IDE-like features for VHDL (similar to my other plugin for SystemVerilog) :

Compare to the basic VHDL plugin it already proposes:

  • a proper symbol definition for easy code navigation
  • Some basic indentation definition
  • A complete set of snippets written by https://github.com/ccornish
  • Tooltip to get signal definition on mouse hover
  • Generate a design hierarchy (list of every sub-block) (available in the command panel)

Future features includes code completion (for record, enum, …), code alignement, block instantiation, …

Description

Syntax Highlighting:

Syntax highlighting is based on the VHDL bundle for Textmate, with a rework of scope to be aligned with the SystemVerilog plugin and some support of VHDL2008 features

Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://bitbucket.org/Clams/sublimesystemverilog/downloads/Sunburst2.tmTheme

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Show hierarchy of a block (all its sub-block and their sub-block)

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection

Code Alignement:

  • Align module instantiation

Configuration

To see all existing configuration option, go to Preferences->Package Settings->SmartVHDL->Settings (Default).

To edit settings open the Settings (User), and add parameter with the value you want.

Keymapping example

To map key to the different feature, simply add the following to your user .sublime-keymap file:

{
        "keys": ["ctrl+f10"], "command": "vhdl_module_inst",
        "context":
        [
            { "key": "num_selections", "operator": "equal", "operand": 1 },
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["ctrl+shift+a"], "command": "vhdl_align",
        "context":
        [
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },