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Smart VHDL

by TheClams ST3

Syntax Highlighting, Snippets, code navigation and more for VHDL

Details

Installs

  • Total 4K
  • Win 3K
  • OS X 426
  • Linux 1K
Jun 19 Jun 18 Jun 17 Jun 16 Jun 15 Jun 14 Jun 13 Jun 12 Jun 11 Jun 10 Jun 9 Jun 8 Jun 7 Jun 6 Jun 5 Jun 4 Jun 3 Jun 2 Jun 1 May 31 May 30 May 29 May 28 May 27 May 26 May 25 May 24 May 23 May 22 May 21 May 20 May 19 May 18 May 17 May 16 May 15 May 14 May 13 May 12 May 11 May 10 May 9 May 8 May 7 May 6 May 5
Windows 0 3 0 3 2 4 2 6 4 4 0 3 1 6 6 8 7 1 1 4 8 2 5 3 0 3 2 5 6 5 1 2 5 5 3 6 2 4 1 2 4 3 7 3 2 1
OS X 0 0 2 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 2 0 1 0 0 2 1 0 1 1 0 1 0 0 0 0 0 1 0 0 0
Linux 1 1 2 0 0 2 3 2 3 2 3 1 1 2 1 2 1 1 1 1 2 3 4 2 0 0 2 4 1 3 2 2 0 1 3 2 6 4 1 0 1 1 3 2 0 2

Readme

Source
raw.​githubusercontent.​com

Sublime Text 'Smart' VHDL Package

General

The goal of this plugin is to provide IDE-like features for VHDL (similar to my other plugin for SystemVerilog) :

Compare to the basic VHDL plugin it already proposes:

  • a proper symbol definition for easy code navigation
  • Some basic indentation definition
  • A complete set of snippets written by https://github.com/ccornish
  • Tooltip to get signal definition on mouse hover
  • Generate a design hierarchy (list of every sub-block) (available in the command panel)

Future features includes code completion (for record, enum, …), code alignement, block instantiation, …

Description

Syntax Highlighting:

Syntax highlighting is based on the VHDL bundle for Textmate, with a rework of scope to be aligned with the SystemVerilog plugin and some support of VHDL2008 features

Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://bitbucket.org/Clams/sublimesystemverilog/downloads/Sunburst2.tmTheme

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Show hierarchy of a block (all its sub-block and their sub-block)
  • Find Instances: find all instance of a module inside a project

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection

Code Alignement:

  • Align module instantiation

Configuration

To see all existing configuration option, go to Preferences->Package Settings->SmartVHDL->Settings (Default).

To edit settings open the Settings (User), and add parameter with the value you want.

Keymapping example

To map key to the different feature, simply add the following to your user .sublime-keymap file:

{
        "keys": ["ctrl+f10"], "command": "vhdl_module_inst",
        "context":
        [
            { "key": "num_selections", "operator": "equal", "operand": 1 },
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["ctrl+shift+a"], "command": "vhdl_align",
        "context":
        [
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["ctrl+alt+f"], "command": "vhdl_find_instance",
        "context":
        [
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["f12"], "command": "vhdl_hierarchy_goto_definition",
        "context":[
            { "key": "selector", "operator": "equal", "operand": "text.result-vhdl"}
        ]
    }