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Smart VHDL

by TheClams ST3

Syntax Highlighting, Snippets, code navigation and more for VHDL

Details

Installs

  • Total 1K
  • Win 695
  • OS X 129
  • Linux 270
Nov 24 Nov 23 Nov 22 Nov 21 Nov 20 Nov 19 Nov 18 Nov 17 Nov 16 Nov 15 Nov 14 Nov 13 Nov 12 Nov 11 Nov 10 Nov 9 Nov 8 Nov 7 Nov 6 Nov 5 Nov 4 Nov 3 Nov 2 Nov 1 Oct 31 Oct 30 Oct 29 Oct 28 Oct 27 Oct 26 Oct 25 Oct 24 Oct 23 Oct 22 Oct 21 Oct 20 Oct 19 Oct 18 Oct 17 Oct 16 Oct 15 Oct 14 Oct 13 Oct 12 Oct 11 Oct 10
Windows 2 8 6 3 5 8 6 5 6 6 5 4 4 4 9 7 4 2 5 1 1 6 5 4 4 13 5 3 10 4 11 6 5 5 4 1 7 7 9 5 0 5 6 2 4 8
OS X 1 0 3 3 1 1 0 2 0 0 1 3 2 0 2 1 0 3 2 1 1 0 1 0 2 0 2 0 1 2 0 1 0 3 0 0 1 1 2 1 0 0 2 0 2 1
Linux 0 5 0 1 2 2 1 1 5 1 4 1 0 3 1 1 1 2 3 2 1 2 4 2 4 4 0 4 3 2 2 5 1 3 0 1 9 2 6 3 0 1 4 5 1 4

Readme

Source
raw.​githubusercontent.​com

Sublime Text 'Smart' VHDL Package

General

The goal of this plugin is to provide IDE-like features for VHDL (similar to my other plugin for SystemVerilog) :

Compare to the basic VHDL plugin it already proposes:

  • a proper symbol definition for easy code navigation
  • Some basic indentation definition
  • A complete set of snippets written by https://github.com/ccornish
  • Tooltip to get signal definition on mouse hover
  • Generate a design hierarchy (list of every sub-block) (available in the command panel)

Future features includes code completion (for record, enum, …), code alignement, block instantiation, …

Description

Syntax Highlighting:

Syntax highlighting is based on the VHDL bundle for Textmate, with a rework of scope to be aligned with the SystemVerilog plugin and some support of VHDL2008 features

Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://bitbucket.org/Clams/sublimesystemverilog/downloads/Sunburst2.tmTheme

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Show hierarchy of a block (all its sub-block and their sub-block)

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection

Code Alignement:

  • Align module instantiation

Configuration

To see all existing configuration option, go to Preferences->Package Settings->SmartVHDL->Settings (Default).

To edit settings open the Settings (User), and add parameter with the value you want.

Keymapping example

To map key to the different feature, simply add the following to your user .sublime-keymap file:

{
        "keys": ["ctrl+f10"], "command": "vhdl_module_inst",
        "context":
        [
            { "key": "num_selections", "operator": "equal", "operand": 1 },
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["ctrl+shift+a"], "command": "vhdl_align",
        "context":
        [
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["f12"], "command": "vhdl_hierarchy_goto_definition",
        "context":[
            { "key": "selector", "operator": "equal", "operand": "text.result-vhdl"}
        ]
    }