Smart VHDL
Syntax Highlighting, Snippets, code navigation and more for VHDL
Details
Installs
- Total 10K
- Win 7K
- Mac 892
- Linux 3K
Jul 27 | Jul 26 | Jul 25 | Jul 24 | Jul 23 | Jul 22 | Jul 21 | Jul 20 | Jul 19 | Jul 18 | Jul 17 | Jul 16 | Jul 15 | Jul 14 | Jul 13 | Jul 12 | Jul 11 | Jul 10 | Jul 9 | Jul 8 | Jul 7 | Jul 6 | Jul 5 | Jul 4 | Jul 3 | Jul 2 | Jul 1 | Jun 30 | Jun 29 | Jun 28 | Jun 27 | Jun 26 | Jun 25 | Jun 24 | Jun 23 | Jun 22 | Jun 21 | Jun 20 | Jun 19 | Jun 18 | Jun 17 | Jun 16 | Jun 15 | Jun 14 | Jun 13 | Jun 12 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Windows | 0 | 1 | 1 | 2 | 1 | 3 | 0 | 0 | 4 | 3 | 2 | 2 | 0 | 1 | 1 | 2 | 2 | 1 | 1 | 5 | 0 | 1 | 3 | 1 | 2 | 3 | 0 | 0 | 3 | 5 | 2 | 1 | 1 | 0 | 1 | 4 | 0 | 3 | 2 | 1 | 2 | 0 | 2 | 0 | 1 | 2 |
Mac | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
Linux | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | 2 | 0 | 1 | 1 | 3 | 2 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 1 | 1 | 0 | 2 |
Readme
- Source
- raw.githubusercontent.com
Sublime Text 'Smart' VHDL Package
General
The goal of this plugin is to provide IDE-like features for VHDL (similar to my other plugin for SystemVerilog) :
Compare to the basic VHDL plugin it already proposes:
- a proper symbol definition for easy code navigation
- Some basic indentation definition
- A complete set of snippets written by https://github.com/ccornish
- Tooltip to get signal definition on mouse hover
- Generate a design hierarchy (list of every sub-block) (available in the command panel)
- Navigation side-bar:
- Display instances/procedure/functions inside the current module/package
- Double click on instance/type to jump to it
Future features includes code completion (for record, enum, …), code alignement, block instantiation, …
Description
Syntax Highlighting:
Syntax highlighting is based on the VHDL bundle for Textmate, with a rework of scope to be aligned with the SystemVerilog plugin and some support of VHDL2008 features
Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://bitbucket.org/Clams/sublimesystemverilog/downloads/Sunburst2.tmTheme
Code Navigation:
- Show signal declaration in tooltip or status bar
- Show hierarchy of a block (all its sub-block and their sub-block)
- Find Instances: find all instance of a module inside a project
Module Instance helper:
- Instantiation: Select a module from a list and create instantiation and connection
Code Alignement:
- Align module instantiation
Configuration
To see all existing configuration option, go to Preferences->Package Settings->SmartVHDL->Settings (Default).
To edit settings open the Settings (User), and add parameter with the value you want.
Keymapping example
To map key to the different feature, simply add the following to your user .sublime-keymap file:
{
"keys": ["ctrl+f10"], "command": "vhdl_module_inst",
"context":
[
{ "key": "num_selections", "operator": "equal", "operand": 1 },
{ "key": "selector", "operator": "equal", "operand": "source.vhdl"}
]
},
{
"keys": ["ctrl+shift+a"], "command": "vhdl_align",
"context":
[
{ "key": "selector", "operator": "equal", "operand": "source.vhdl"}
]
},
{
"keys": ["ctrl+alt+f"], "command": "vhdl_find_instance",
"context":
[
{ "key": "selector", "operator": "equal", "operand": "source.vhdl"}
]
},
{
"keys": ["f12"], "command": "vhdl_hierarchy_goto_definition",
"context":[
{ "key": "selector", "operator": "equal", "operand": "text.result-vhdl"}
]
},
{ "keys": ["f1"], "command": "vhdl_toggle_navbar", "args":{"cmd":"toggle"}},
{ "keys": ["ctrl+f1"], "command": "vhdl_toggle_lock_navbar"},
{
"keys": ["alt+f1"], "command": "vhdl_show_navbar",
"context":[{ "key": "selector", "operator": "equal", "operand": "source.vhdl"}]
}