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Smart VHDL

by TheClams ST3

Syntax Highlighting, Snippets, code navigation and more for VHDL

Details

Installs

  • Total 3K
  • Win 2K
  • OS X 274
  • Linux 676
Aug 15 Aug 14 Aug 13 Aug 12 Aug 11 Aug 10 Aug 9 Aug 8 Aug 7 Aug 6 Aug 5 Aug 4 Aug 3 Aug 2 Aug 1 Jul 31 Jul 30 Jul 29 Jul 28 Jul 27 Jul 26 Jul 25 Jul 24 Jul 23 Jul 22 Jul 21 Jul 20 Jul 19 Jul 18 Jul 17 Jul 16 Jul 15 Jul 14 Jul 13 Jul 12 Jul 11 Jul 10 Jul 9 Jul 8 Jul 7 Jul 6 Jul 5 Jul 4 Jul 3 Jul 2 Jul 1
Windows 0 5 4 0 1 3 2 2 2 3 3 3 3 4 2 9 3 1 1 5 4 3 6 3 0 4 3 2 3 4 4 2 0 3 4 6 8 3 2 0 3 7 1 10 4 3
OS X 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 2 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Linux 0 2 5 0 0 2 1 1 1 2 0 0 0 1 2 0 1 1 2 4 7 0 2 4 2 1 2 0 3 1 2 0 0 4 1 6 4 1 0 1 2 3 3 6 3 1

Readme

Source
raw.​githubusercontent.​com

Sublime Text 'Smart' VHDL Package

General

The goal of this plugin is to provide IDE-like features for VHDL (similar to my other plugin for SystemVerilog) :

Compare to the basic VHDL plugin it already proposes:

  • a proper symbol definition for easy code navigation
  • Some basic indentation definition
  • A complete set of snippets written by https://github.com/ccornish
  • Tooltip to get signal definition on mouse hover
  • Generate a design hierarchy (list of every sub-block) (available in the command panel)

Future features includes code completion (for record, enum, …), code alignement, block instantiation, …

Description

Syntax Highlighting:

Syntax highlighting is based on the VHDL bundle for Textmate, with a rework of scope to be aligned with the SystemVerilog plugin and some support of VHDL2008 features

Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://bitbucket.org/Clams/sublimesystemverilog/downloads/Sunburst2.tmTheme

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Show hierarchy of a block (all its sub-block and their sub-block)
  • Find Instances: find all instance of a module inside a project

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection

Code Alignement:

  • Align module instantiation

Configuration

To see all existing configuration option, go to Preferences->Package Settings->SmartVHDL->Settings (Default).

To edit settings open the Settings (User), and add parameter with the value you want.

Keymapping example

To map key to the different feature, simply add the following to your user .sublime-keymap file:

{
        "keys": ["ctrl+f10"], "command": "vhdl_module_inst",
        "context":
        [
            { "key": "num_selections", "operator": "equal", "operand": 1 },
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["ctrl+shift+a"], "command": "vhdl_align",
        "context":
        [
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["ctrl+alt+f"], "command": "vhdl_find_instance",
        "context":
        [
            { "key": "selector", "operator": "equal", "operand": "source.vhdl"}
        ]
    },
    {
        "keys": ["f12"], "command": "vhdl_hierarchy_goto_definition",
        "context":[
            { "key": "selector", "operator": "equal", "operand": "text.result-vhdl"}
        ]
    }