Smart VHDL
Syntax Highlighting, Snippets, code navigation and more for VHDL
Details
Installs
- Total 11K
- Win 7K
- Mac 935
- Linux 3K
May 6 | May 5 | May 4 | May 3 | May 2 | May 1 | Apr 30 | Apr 29 | Apr 28 | Apr 27 | Apr 26 | Apr 25 | Apr 24 | Apr 23 | Apr 22 | Apr 21 | Apr 20 | Apr 19 | Apr 18 | Apr 17 | Apr 16 | Apr 15 | Apr 14 | Apr 13 | Apr 12 | Apr 11 | Apr 10 | Apr 9 | Apr 8 | Apr 7 | Apr 6 | Apr 5 | Apr 4 | Apr 3 | Apr 2 | Apr 1 | Mar 31 | Mar 30 | Mar 29 | Mar 28 | Mar 27 | Mar 26 | Mar 25 | Mar 24 | Mar 23 | Mar 22 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Windows | 1 | 0 | 1 | 0 | 0 | 1 | 4 | 2 | 1 | 0 | 0 | 1 | 2 | 2 | 2 | 3 | 2 | 1 | 0 | 4 | 1 | 1 | 2 | 2 | 1 | 0 | 1 | 2 | 0 | 1 | 0 | 0 | 1 | 1 | 2 | 2 | 0 | 1 | 1 | 0 | 1 | 1 | 3 | 2 | 0 | 0 |
Mac | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
Linux | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 0 | 1 | 0 | 0 | 0 |
Readme
- Source
- raw.githubusercontent.com
Sublime Text 'Smart' VHDL Package
General
The goal of this plugin is to provide IDE-like features for VHDL (similar to my other plugin for SystemVerilog) :
Compare to the basic VHDL plugin it already proposes:
- a proper symbol definition for easy code navigation
- Some basic indentation definition
- A complete set of snippets written by https://github.com/ccornish
- Tooltip to get signal definition on mouse hover
- Generate a design hierarchy (list of every sub-block) (available in the command panel)
- Navigation side-bar:
- Display instances/procedure/functions inside the current module/package
- Double click on instance/type to jump to it
Future features includes code completion (for record, enum, …), code alignement, block instantiation, …
Description
Syntax Highlighting:
Syntax highlighting is based on the VHDL bundle for Textmate, with a rework of scope to be aligned with the SystemVerilog plugin and some support of VHDL2008 features
Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://bitbucket.org/Clams/sublimesystemverilog/downloads/Sunburst2.tmTheme
Code Navigation:
- Show signal declaration in tooltip or status bar
- Show hierarchy of a block (all its sub-block and their sub-block)
- Find Instances: find all instance of a module inside a project
Module Instance helper:
- Instantiation: Select a module from a list and create instantiation and connection
Code Alignement:
- Align module instantiation
Configuration
To see all existing configuration option, go to Preferences->Package Settings->SmartVHDL->Settings (Default).
To edit settings open the Settings (User), and add parameter with the value you want.
Keymapping example
To map key to the different feature, simply add the following to your user .sublime-keymap file:
{
"keys": ["ctrl+f10"], "command": "vhdl_module_inst",
"context":
[
{ "key": "num_selections", "operator": "equal", "operand": 1 },
{ "key": "selector", "operator": "equal", "operand": "source.vhdl"}
]
},
{
"keys": ["ctrl+shift+a"], "command": "vhdl_align",
"context":
[
{ "key": "selector", "operator": "equal", "operand": "source.vhdl"}
]
},
{
"keys": ["ctrl+alt+f"], "command": "vhdl_find_instance",
"context":
[
{ "key": "selector", "operator": "equal", "operand": "source.vhdl"}
]
},
{
"keys": ["f12"], "command": "vhdl_hierarchy_goto_definition",
"context":[
{ "key": "selector", "operator": "equal", "operand": "text.result-vhdl"}
]
},
{ "keys": ["f1"], "command": "vhdl_toggle_navbar", "args":{"cmd":"toggle"}},
{ "keys": ["ctrl+f1"], "command": "vhdl_toggle_lock_navbar"},
{
"keys": ["alt+f1"], "command": "vhdl_show_navbar",
"context":[{ "key": "selector", "operator": "equal", "operand": "source.vhdl"}]
}