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System​Verilog

by TheClams ST2/ST3

Syntax Highlighting, smart snippets, autocompletion, code navigation and more for Verilog and SystemVerilog

Details

Installs

  • Total 15K
  • Win 9K
  • OS X 3K
  • Linux 4K
Oct 19 Oct 18 Oct 17 Oct 16 Oct 15 Oct 14 Oct 13 Oct 12 Oct 11 Oct 10 Oct 9 Oct 8 Oct 7 Oct 6 Oct 5 Oct 4 Oct 3 Oct 2 Oct 1 Sep 30 Sep 29 Sep 28 Sep 27 Sep 26 Sep 25 Sep 24 Sep 23 Sep 22 Sep 21 Sep 20 Sep 19 Sep 18 Sep 17 Sep 16 Sep 15 Sep 14 Sep 13 Sep 12 Sep 11 Sep 10 Sep 9 Sep 8 Sep 7 Sep 6 Sep 5 Sep 4
Windows 19 17 16 28 5 8 21 19 15 19 19 13 12 10 22 15 23 16 16 9 16 19 15 14 20 7 12 24 21 18 20 22 14 15 16 29 28 21 9 3 8 15 25 13 12 12
OS X 5 2 6 5 5 5 4 5 3 8 5 2 3 5 3 4 7 6 4 2 10 3 4 6 5 0 1 6 8 7 6 7 4 3 7 13 6 4 2 1 1 1 2 4 6 0
Linux 14 8 6 10 4 3 8 12 8 13 5 7 0 7 11 8 9 9 7 4 10 11 12 9 9 6 1 2 6 15 13 15 7 9 14 10 4 12 13 6 5 7 4 7 11 11

Readme

Source
raw.​githubusercontent.​com

Sublime Text SystemVerilog Package

Description

Syntax Highlighting:

  • SystemVerilog / Verilog
  • UCF (Xilinx Constraint file)

Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://bitbucket.org/Clams/sublimesystemverilog/downloads/Sunburst2.tmTheme

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Goto declaration : move cursor to the declaration of the selected signal
  • Goto driver : select a signal a go to the driver (port, assignement, connection)
  • Find Instances: find all instance of a module inside a project
  • Show hierarchy of a module (all its sub-module)
  • Move cursor / select text between start/end of block (like [], {}, begin/end, function/endfunction, …)

Code Completion :

  • Smart Autocompletion: method for standard type, field for struct/interface/class, system task, …
  • Smart snippet for always, case
  • 'begin end' macro to surround a text by begin/end (cf Keymapping section to see how to use it)
  • Various Snippets (module, interface, class, for, …)
  • Insert template for FSM

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection
  • Reconnect: remove connection to deleted port, add connection to new port
  • Toggle .* in module binding (similar to the auto-star feature of Emacs verilog-mode)

Code Alignement:

  • Reindent
  • Align module port
  • Align signal declaration
  • Align module instantiation
  • Align assignement

Linting:

  • Find/Remove all unused signals
  • List all undeclared signals

Configuration

To see all existing configuration option, go to Preferences->Package Settings->SystemVerilog->Settings (Default).

To edit settings open the Settings (User), and add parameter with the value you want.

Detail documentation

For a detail documentation on the different features, check online documentation: http://sv-doc.readthedocs.org/en/latest .

Keymapping example

To map key to the different feature, simply add the following to your user .sublime-keymap file:

{
    "keys": ["f10"], "command": "verilog_type",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f10"], "command": "verilog_module_inst",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+f10"], "command": "verilog_toggle_dot_star",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+a"], "command": "verilog_align",
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["alt+shift+a"], "command": "verilog_align", "args":{"cmd":"reindent"},
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f12"], "command": "verilog_goto_driver",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["shift+f12"], "command": "verilog_goto_declaration",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
// Begin/End
{
    "keys": ["ctrl+'"],
    "command": "insert_snippet", "args": {"contents": "begin\n\t$0\nend"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": true, "match_all": true }]
},
{
    "keys": ["ctrl+'"],
    "command": "run_macro_file",
    "args": {"file": "Packages/SystemVerilog/beginend.sublime-macro"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": false, "match_all": true }]
},
{
    "keys": ["ctrl+m"], "command": "verilog_goto_block_boundary", "args":{"cmd":"move"},
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+m"], "command": "verilog_goto_block_boundary", "args":{"cmd":"select"},
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
}