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System​Verilog

by TheClams ALL

Syntax Highlighting, smart snippets, autocompletion, code navigation and more for Verilog and SystemVerilog

Details

Installs

  • Total 63K
  • Win 39K
  • Mac 9K
  • Linux 15K
Dec 21 Dec 20 Dec 19 Dec 18 Dec 17 Dec 16 Dec 15 Dec 14 Dec 13 Dec 12 Dec 11 Dec 10 Dec 9 Dec 8 Dec 7 Dec 6 Dec 5 Dec 4 Dec 3 Dec 2 Dec 1 Nov 30 Nov 29 Nov 28 Nov 27 Nov 26 Nov 25 Nov 24 Nov 23 Nov 22 Nov 21 Nov 20 Nov 19 Nov 18 Nov 17 Nov 16 Nov 15 Nov 14 Nov 13 Nov 12 Nov 11 Nov 10 Nov 9 Nov 8 Nov 7 Nov 6
Windows 4 6 4 13 3 6 5 6 8 9 11 12 14 8 4 8 5 9 14 13 4 11 10 5 0 0 0 0 10 10 8 5 5 13 9 13 12 0 0 8 10 5 1 7 12 10
Mac 0 0 2 1 0 0 0 1 4 3 2 1 3 1 0 3 2 1 2 1 1 0 1 0 0 0 0 1 0 1 1 0 0 2 2 0 1 0 0 2 3 3 2 1 1 2
Linux 0 1 9 13 3 3 2 2 0 5 5 7 8 3 3 1 5 7 6 8 3 1 6 1 0 0 0 0 3 4 6 4 2 6 4 4 6 0 0 15 6 2 4 11 7 11

Readme

Source
raw.​githubusercontent.​com

Sublime Text SystemVerilog Package

Description

Syntax Highlighting:

  • SystemVerilog / Verilog
  • UCF (Xilinx Constraint file)

Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://gist.github.com/TheClams/5811d7bc8829abe58c11d4c98e729dc0

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Goto declaration : move cursor to the declaration of the selected signal
  • Goto driver : select a signal a go to the driver (port, assignement, connection)
  • Find Instances: find all instance of a module inside a project
  • Move cursor / select text between start/end of block (like [], {}, begin/end, function/endfunction, …)
  • Show hierarchy of a module (all its sub-module)
  • Navigation side-bar:
    • Displaying a class members/method, module port/signal/instances, …
    • Double click on instance/type to jump to it

Code Completion :

  • Smart Autocompletion: method for standard type, field for struct/interface/class, system task, …
  • Smart snippet for always, case
  • 'begin end' macro to surround a text by begin/end (cf Keymapping section to see how to use it)
  • Various Snippets (module, interface, class, for, …)
  • Insert template for FSM

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection
  • Reconnect: remove connection to deleted port, add connection to new port
  • Toggle .* in module binding (similar to the auto-star feature of Emacs verilog-mode)

Code Alignement:

  • Reindent
  • Align module port
  • Align signal declaration
  • Align module instantiation
  • Align assignement

Linting:

  • Find/Remove all unused signals
  • List all undeclared signals

Configuration

To see all existing configuration option and edit your configuration, go to Preferences->Package Settings->SystemVerilog->Settings.

Detail documentation

For a detail documentation on the different features, check online documentation: http://sv-doc.readthedocs.org/en/latest .

Keymapping example

To map key to the different features, simply add the following to your user .sublime-keymap file:

{
    "keys": ["f10"], "command": "verilog_type",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f10"], "command": "verilog_module_inst",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+f10"], "command": "verilog_toggle_dot_star",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+a"], "command": "verilog_align",
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["alt+shift+a"], "command": "verilog_align", "args":{"cmd":"reindent"},
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f12"], "command": "verilog_goto_driver",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["shift+f12"], "command": "verilog_goto_declaration",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
// Begin/End
{
    "keys": ["ctrl+'"],
    "command": "insert_snippet", "args": {"contents": "begin\n\t$0\nend"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": true, "match_all": true }]
},
{
    "keys": ["ctrl+'"],
    "command": "run_macro_file",
    "args": {"file": "Packages/SystemVerilog/beginend.sublime-macro"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": false, "match_all": true }]
},
{
    "keys": ["ctrl+m"], "command": "verilog_goto_block_boundary", "args":{"cmd":"move"},
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+m"], "command": "verilog_goto_block_boundary", "args":{"cmd":"select"},
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{ "keys": ["f1"], "command": "verilog_toggle_navbar", "args":{"cmd":"toggle"}},
{ "keys": ["ctrl+f1"], "command": "verilog_toggle_lock_navbar"},
{
  "keys": ["alt+f1"], "command": "verilog_show_navbar",
  "context":[{ "key": "selector", "operator": "equal", "operand": "source.systemverilog"}]
}