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System​Verilog

by TheClams ALL

Syntax Highlighting, smart snippets, autocompletion, code navigation and more for Verilog and SystemVerilog

Details

Installs

  • Total 40K
  • Win 23K
  • Mac 7K
  • Linux 10K
Mar 9 Mar 8 Mar 7 Mar 6 Mar 5 Mar 4 Mar 3 Mar 2 Mar 1 Feb 28 Feb 27 Feb 26 Feb 25 Feb 24 Feb 23 Feb 22 Feb 21 Feb 20 Feb 19 Feb 18 Feb 17 Feb 16 Feb 15 Feb 14 Feb 13 Feb 12 Feb 11 Feb 10 Feb 9 Feb 8 Feb 7 Feb 6 Feb 5 Feb 4 Feb 3 Feb 2 Feb 1 Jan 31 Jan 30 Jan 29 Jan 28 Jan 27 Jan 26 Jan 25 Jan 24 Jan 23
Windows 9 21 12 11 22 18 14 23 12 15 15 13 20 15 28 20 9 7 10 12 16 16 17 9 13 11 9 15 23 13 16 8 15 20 20 17 28 9 11 25 20 20 23 22 8 17
Mac 1 3 2 0 5 6 6 3 0 1 3 2 1 1 1 3 3 3 4 3 2 2 5 2 2 4 1 2 3 2 2 3 2 2 3 6 3 1 6 2 2 3 2 3 4 1
Linux 2 9 3 2 9 8 11 12 7 5 2 5 10 17 6 15 5 7 7 13 14 6 9 2 1 6 7 5 11 12 6 4 7 7 15 10 9 10 7 5 5 3 15 13 5 1

Readme

Source
raw.​githubusercontent.​com

Sublime Text SystemVerilog Package

Description

Syntax Highlighting:

  • SystemVerilog / Verilog
  • UCF (Xilinx Constraint file)

Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://gist.github.com/TheClams/5811d7bc8829abe58c11d4c98e729dc0

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Goto declaration : move cursor to the declaration of the selected signal
  • Goto driver : select a signal a go to the driver (port, assignement, connection)
  • Find Instances: find all instance of a module inside a project
  • Move cursor / select text between start/end of block (like [], {}, begin/end, function/endfunction, …)
  • Show hierarchy of a module (all its sub-module)
  • Navigation side-bar:
    • Displaying a class members/method, module port/signal/instances, …
    • Double click on instance/type to jump to it

Code Completion :

  • Smart Autocompletion: method for standard type, field for struct/interface/class, system task, …
  • Smart snippet for always, case
  • 'begin end' macro to surround a text by begin/end (cf Keymapping section to see how to use it)
  • Various Snippets (module, interface, class, for, …)
  • Insert template for FSM

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection
  • Reconnect: remove connection to deleted port, add connection to new port
  • Toggle .* in module binding (similar to the auto-star feature of Emacs verilog-mode)

Code Alignement:

  • Reindent
  • Align module port
  • Align signal declaration
  • Align module instantiation
  • Align assignement

Linting:

  • Find/Remove all unused signals
  • List all undeclared signals

Configuration

To see all existing configuration option and edit your configuration, go to Preferences->Package Settings->SystemVerilog->Settings.

Detail documentation

For a detail documentation on the different features, check online documentation: http://sv-doc.readthedocs.org/en/latest .

Keymapping example

To map key to the different features, simply add the following to your user .sublime-keymap file:

{
    "keys": ["f10"], "command": "verilog_type",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f10"], "command": "verilog_module_inst",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+f10"], "command": "verilog_toggle_dot_star",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+a"], "command": "verilog_align",
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["alt+shift+a"], "command": "verilog_align", "args":{"cmd":"reindent"},
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f12"], "command": "verilog_goto_driver",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["shift+f12"], "command": "verilog_goto_declaration",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
// Begin/End
{
    "keys": ["ctrl+'"],
    "command": "insert_snippet", "args": {"contents": "begin\n\t$0\nend"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": true, "match_all": true }]
},
{
    "keys": ["ctrl+'"],
    "command": "run_macro_file",
    "args": {"file": "Packages/SystemVerilog/beginend.sublime-macro"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": false, "match_all": true }]
},
{
    "keys": ["ctrl+m"], "command": "verilog_goto_block_boundary", "args":{"cmd":"move"},
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+m"], "command": "verilog_goto_block_boundary", "args":{"cmd":"select"},
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{ "keys": ["f1"], "command": "verilog_toggle_navbar", "args":{"cmd":"toggle"}},
{ "keys": ["ctrl+f1"], "command": "verilog_toggle_lock_navbar"},
{
  "keys": ["alt+f1"], "command": "verilog_show_navbar",
  "context":[{ "key": "selector", "operator": "equal", "operand": "source.systemverilog"}]
}