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Verilog Gadget

by poucotm ST2/ST3

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

Labels verilog

Details

Installs

  • Total 4K
  • Win 3K
  • OS X 503
  • Linux 808
Aug 24 Aug 23 Aug 22 Aug 21 Aug 20 Aug 19 Aug 18 Aug 17 Aug 16 Aug 15 Aug 14 Aug 13 Aug 12 Aug 11 Aug 10 Aug 9 Aug 8 Aug 7 Aug 6 Aug 5 Aug 4 Aug 3 Aug 2 Aug 1 Jul 31 Jul 30 Jul 29 Jul 28 Jul 27 Jul 26 Jul 25 Jul 24 Jul 23 Jul 22 Jul 21 Jul 20 Jul 19 Jul 18 Jul 17 Jul 16 Jul 15 Jul 14 Jul 13 Jul 12 Jul 11 Jul 10
Windows 2 5 2 5 5 2 6 1 4 7 4 6 2 3 5 6 4 4 8 5 3 2 3 3 6 2 4 2 1 3 3 5 9 4 3 3 3 5 9 4 4 2 4 3 7 3
OS X 0 0 0 1 1 0 2 2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 2 0 1 1 1 1 0 1 0 0 0 0 0
Linux 0 1 0 3 0 2 0 1 1 1 3 3 1 0 1 0 0 0 0 0 1 0 2 0 0 1 1 0 1 3 3 1 3 4 0 0 0 0 0 2 2 1 1 0 1 2

Readme

Source
raw.​githubusercontent.​com

Verilog Gadget for Sublime Text

Package Control PayPal

Use Verilog Gadget Commands in command palette (ctrl+shift+p) or context menu to run. The context menu only can be seen for .v, .vh, .sv, .svh file. (file extensions can be added or changed in settings). The theme is Guna, which is used in examples. There's a linter plug-in for Verilog. SublimeLinter-contrib-verilator

Verilog Gadget: Instantiate Module (ctrl+shift+c)

  • It parses module ports in currently open file
  • It generates module's instance text
  • It copies generated text to clipboard
  • You can paste the text on where you want
  • Supports Verilog-1995, Verilog-2001 style ports and parameters
  • example)

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Verilog Gadget: Generate Testbench

  • It parses module ports in currently open file
  • It generates a simple testbench with module's instance and signals
  • Testbench will be generated as a systemverilog file
  • Supports Verilog-1995, Verilog-2001 style ports and parameters
  • example)

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Verilog Gadget: Insert Header (ctrl+shift+insert)

  • You can insert your own header-description as your format from the file specified in settings
  • {YEAR} will be replaced as this year
  • {DATE} will be replaced as create date
  • {TIME} will be replaced as create time
  • {RDATE} will be replaced as revised date
  • {RTIME} will be replaced as revised time
  • {FILE} will be replaced as file name
  • {TABS} will be replaced as tab size
  • {SUBLIME_VERSION} will be replaced as current sublime text version
  • example) header example

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Verilog Gadget: Repeat Code with Numbers (ctrl+f12)

  • Select codes to be repeated, it may include Python's format symbol like {…}
  • Type a range in the input panel as the following : [from]~[to],[↓step],[→step] (e.g. 0~10 or 0~10,2 or 10~0,-1 or 0~5,1,1 ...)
  • [↓step] means row step, default is 1, [→step] means column step, default is 0
  • The codes will be repeated with incremental or decremental numbers
  • Python's format symbol supports variable formats : binary, hex, leading zeros, …
  • To use '{' as is, you should type twice as '{{'
  • Refer to Python's format symbol here, https://www.python.org/dev/peps/pep-3101/
  • For sublime text 2 (python 2.x), you should insert index behind of ':' in curly brackets like foo {0:5b} bar {1:3d}
  • example)

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  • The index can be used in order to repeat the same number
  • example)

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  • It is possible to repeat numbers with clipboard text (line by line)
  • Use {cb} for clipboard text
  • example)

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Verilog Gadget: Alignment (ctrl+shift+x)

  • Select range to apply alignment
  • Press the shortcut key
  • Alignment is based on the longest length of left hand side in selection
  • Tabs will be replaced as spaces except for indent
  • example)

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Verilog Gadget: Insert Snippet (ctrl+alt+p)

  • You can make your own parameterized snippets like this example
  • Add your snippet settings like this
  • Run Insert Snippet command
  • example)

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Verilog Linter (another package)

SublimeLinter-contrib-verilator

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Donate

Doate Image

Thank you for donating. It is helpful to continue to improve the plug-in.

Issues

When you have an issue, tell me through https://github.com/poucotm/Verilog-Gadget/issues, or send me an e-mail poucotm@gmail.com