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Verilog Gadget

by poucotm ALL

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

Labels verilog

Details

Installs

  • Total 11K
  • Win 9K
  • Mac 954
  • Linux 2K
Aug 12 Aug 11 Aug 10 Aug 9 Aug 8 Aug 7 Aug 6 Aug 5 Aug 4 Aug 3 Aug 2 Aug 1 Jul 31 Jul 30 Jul 29 Jul 28 Jul 27 Jul 26 Jul 25 Jul 24 Jul 23 Jul 22 Jul 21 Jul 20 Jul 19 Jul 18 Jul 17 Jul 16 Jul 15 Jul 14 Jul 13 Jul 12 Jul 11 Jul 10 Jul 9 Jul 8 Jul 7 Jul 6 Jul 5 Jul 4 Jul 3 Jul 2 Jul 1 Jun 30 Jun 29 Jun 28
Windows 9 7 11 9 11 4 2 9 9 11 5 13 7 6 11 11 7 16 8 3 4 3 8 10 5 9 4 12 13 20 11 11 8 3 9 14 14 17 9 16 5 12 9 12 8 12
Mac 0 1 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0
Linux 0 3 2 2 0 0 0 1 4 6 1 0 2 1 1 3 1 2 1 1 1 1 2 3 1 1 0 2 0 1 0 0 2 0 0 3 3 1 1 4 0 2 2 3 1 3

Readme

Source
raw.​githubusercontent.​com

Verilog Gadget for Sublime Text

Package Control PayPal

Use Verilog Gadget Commands in command palette (ctrl+shift+p) or context menu to run. The context menu only can be seen for .v, .vh, .sv, .svh file. (file extensions can be added or changed in settings). The theme is Guna, which is used in examples. There's a linter plug-in for Verilog. SublimeLinter-contrib-verilator

Verilog Gadget: Instantiate Module (ctrl+shift+c)

  • It parses module ports for the currently open file
  • It generates an instance text of the module
  • It copies generated text to clipboard
  • Then, you can paste the text to the desired location
  • Supports Verilog-1995, Verilog-2001 style ports and parameters
  • example)

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Verilog Gadget: Generate Testbench

  • It parses module ports for the currently open file
  • It generates a simple testbench with an instance and signals of the module
  • The testbench is created as a systemverilog file
  • Supports Verilog-1995, Verilog-2001 style ports and parameters
  • example)

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Verilog Gadget: Simulaton Template

  • It creates files for simulation based on the template
  • You can make your own template as a compressed file (.zip,.tar,.tgz)
  • You can specify the path of your template ("simulation_template","simulation_directory“)
  • 'example-modelsim' is the template for modelsim, 'example-vcs' is the template for vcs
  • It automatically generates the testbench files for the current view
  • It changes keywords in files of the template ({{TESTBENCH FILE}}, {{TESTBENCH NAME}}, {{MODULE FILE}}, {{MODULE NAME}},{{MODULE PORTLIST}})
  • example)

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Verilog Gadget: Insert Header (ctrl+shift+insert)

  • You can insert your own header-description in a format from the file specified in settings
  • {YEAR} is replaced as the current year
  • {DATE} is replaced as the create date
  • {TIME} is replaced as the create time
  • {RDATE} is replaced as the revised date
  • {RTIME} is replaced as the revised time
  • {FILE} is replaced as the file name
  • {TABS} is replaced as the tab size
  • {SUBLIME_VERSION} is replaced as the current sublime text version
  • example) header example

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Verilog Gadget: Repeat Code with Numbers (ctrl+f12)

  • Select codes you want to repeat, this may include Python's format symbol, such as {…}
  • Enter a range in the input panel as the following : [from]~[to],[↓step],[→step] (e.g. 0~10 or 0~10,2 or 10~0,-1 or 0~5,1,1 ...)
  • [↓step] means the row step, default is 1, [→step] means the column step, default is 0
  • The code is repeated in incremental or decremental numbers
  • Python's format symbol supports variable formats : binary, hex, leading zeros, …
  • To use '{' as it is, you must enter twice like '{{'
  • Refer to Python's format symbol here, https://www.python.org/dev/peps/pep-3101/
  • For sublime text 2 (python 2.x), you must put an index behind ':' in curly brackets like foo {0:5b} bar {1:3d}
  • example)

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  • The index can be used to repeat the same number
  • example)

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  • It is possible to repeat numbers with clipboard text (line by line)
  • Use {cb} for clipboard text
  • example)

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Verilog Gadget: Alignment (ctrl+shift+x)

  • Select a range to apply the alignment to
  • Press the shortcut key
  • Alignment is based on the longest length of the left hand side in the selection
  • Tabs are replaced as spaces except indentation
  • example)

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Verilog Gadget: Insert Snippet (ctrl+alt+p)

  • You can make your own parameterized snippets like this example
  • Add your snippet settings like this
  • Run Insert Snippet command
  • example)

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Verilog Gadget: VCD to WaveDrom (ctrl+alt+v)

  • WaveDrom : digital timing diagram editor
  • Open .vcd file (a clock should be included)
  • Run VCD to WaveDrom command

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Verilog Linter (another package)

SublimeLinter-contrib-verilator

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Donate

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Thank you for donating. It is helpful to continue to improve the plug-in.

Issues

When you have an issue, tell me through https://github.com/poucotm/Verilog-Gadget/issues, or send me an e-mail poucotm@gmail.com